Bejjam Abhishikth

Client: INTEL Technologies Server and Client Chip - 3nm, 5Blocks Roles and Responsibilities: •Resolved DRCs and fixing the violations in ATPG pattern generation for 5 partitions. •Done with test coverage improvement. •Done with call aware, chain disabling and good simulation for some partitions. •Done with one hot pattern, gray box for 5 partitions. •Good knowledge of simulation flow. •Done pattern retargeting for stuck-at and at speed. •Generated test patterns stuck-at & at-speed modes.

Client: MICRON Technologies Server Chip - 7nm, 5 Blocks Roles and Responsibilities: •Resolved Scan DRCs and fixing the violations and implemented scan methodology for 5 partitions. •Done with test coverage improvement. •Generated test patterns stuck-at & at-speed modes. •Validated chain and stuck-at simulations for all patterns. •Performed no-timing and timing simulations and validate the patterns.

Client : MICRON Technologies Networking Chip - 5nm, 4 Blocks Roles and Responsibilities: •Efficiently resolved scan DRC’s. •Debugging the ATPG DRC violations and fixing the violations. •Done Test coverage analysis for all of partitions and reached targeted coverage numbers. •Patterns were simulated with Zero-delay mode & Timing (Min & Max) mode. •Validated chain and stuck-at simulations for all patterns. •Done with one hot pattern, gray box.