Barkha Bhagia
Summer Consultant @ Boston Consulting Group (BCG)
About
Serdes and High Speed IO design Memory Design Custom Memory Layouts Standard Cell Layout Basic Analog Layout Design
United States
Los Angeles
Management Consulting
ASIC, VLSI, RTL coding, Cadence Virtuoso, Physical Design, Semiconductors, Calibre, Cadence Virtuoso XL, Cadence Skill, Cadence, SoC, C, Physical Verification, Analog Circuit Design, Very-Large-Scale Integration (VLSI), Analog, CMOS, Mixed Signal, DRC, EDA
Experience
Summer Consultant
Boston Consulting Group (BCG)
Dallas, Texas, United States
Analog Engineer
Intel
India
Staff Engineer
Samsung Electronics
Staff Engineer
Eximius Design
Bengaluru Area, India
SERDES and High Speed IO circuit design
Staff Design Engineer
Insemi Technology Services Private Limited
Bangalore
Contractor - Layout
AMD
Bengaluru Area, India
1. Custom Memory Layout Design in 20nm,16nm,14nm,7nm -- Layouts of important building blocks like array, sense amp, IO blocks, leaf-cells of Control block. -- Responsible for Physical Verification of the blocks and Macro level. 2. Standard cells in 20nm, 16nm, 14nm
Senior Design Engineer
HCLTech
Bengaluru Area, India
Custom Memory Layout/Mask Design
VLSI Trainee Engineer
HCLTech
Education
USC Marshall School of Business
BITS Pilani Work Integrated Learning Programmes
Microelectronics
Barkha Bhagia's Contact Information
Phone
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