Baheerathan Anandharengan

- Founding member of Infra Silicon team - Key contributor in building the ASIC team from scratch - Led several 0-1 initiatives for the successful ASIC enablement - Led the development of Meta's first successful A0 silicon accelerator to production for Video Transcoding - Technology exploration (cHBM/3D-DRAM/3DSOIC) for the next generation compute scaling - Supporting a broad team of design engineers for building leading Meta Training & Inference Accelerators (MTIA) - Scaled the design team to enable multiple parallel chip developments - Built Design methodology from scratch

- Scalable Video IP Development * * Unified Bit Stream Processor * * Scalable Deblocking Filter Engine * * Computer Vision * * Scalable Video IP Integration - Design Flow Automation * * Developed Perl based Verilog Automation for Verilog Parsing, Auto Declaration, Auto Instantiation, Embedded Perl, Scalable Design Generation and Basic Linting etc... * * RTL Build Flow * * Scalable Design Flow to generate RTL for different tiers from single source - Graphics IP Development * * ALU Design

Ultra Low Power Mobile Application Processors and Companion Chip Development (TEGRA) - Member of Video Decoder IP development Team. Implemented VP8 Feature in the Transform Engine and improved performance for H264/MPEG/JPEG Transformation. - Micro-architected, Implemented Barycentric Clip unit for 3D Graphics used in all generations of Tegra Ultra-Low-Power GPUs. - Micro-architected and Designed JPEG Encoder. - Led Timing Closure Team and successfully taped out multiple chips. - Synthesis/Partitioning/Timing Methodology Setup. - Chip Integration. Integrated Chipset Development for Intel Processors - USB Host Controller Changes. - Design For Debug with On Chip Logic Analyser and Bus Tracers with streaming on USB/JTAG. - Drove system level validation effort. - Integrated GPU Timing Closure. - Synthesis/Partitioning/Timing Methodology Setup. - Silicon Bring up.

Wireless LAN Media Access Controller - Synthesis Setup. - Timing Closure.

Reconfigurable Communications Processor (RCP) - Verification of Data Path Unit. - Static Functional Verification.

USB On-The-Go(OTG) For SoC - Micro-Architecture definition for OTG later and Integration with SoC. - Developed OTG Model. Gigabit Network Controller - Developed VERA Test Environment for the Descriptor Management. - Full Chip Verification. - Timing Closure Effort.

Voice over IP (VoIP) SoC - Micro-architected and Designed Descriptor Based DMA that was used by all the peripherals in the SoC. - USB Device Controller Integration into SoC. - Full Chip Synthesis and TIming Closure. SDRAM Memory Modeling for Phoenix Technologies. - Verilog Model Development. - Verification of SDRAM Models.