Ayush Pathak
Lead Engineer @ HCLTech
About
An enthusiastic spirit with highly motivated and leadership skills. Professionally trained Design Verification Engineer. • High level understanding and knowledge in Verilog, SystemVerilog, SystemVerilog Assertion, Electronics Circuit Design, Digital Electronics, Analog Electronics, Universal Verification Methodology (UVM), DFT. • Hands on experience in developing test bench components. • Strong quality assurance professional with a Bachelor of Technology - BTech focused in Electronics and Communications Engineering from ABES Engineering College.
India
Bengaluru
Semiconductors
AMBA AHB, DDR4, DDR2, DDR3 SDRAM, DDR SDRAM, Service Provider Interface (SPI), System on a Chip (SoC), Toggle, Systems Analysis, Ethernet, Debugging, AXI, Very-Large-Scale Integration (VLSI), Verilog, SystemVerilog, System Verilog Assertions, Analog electronics, Digital Electronics, DFT, Analog Circuit Design
Experience
Lead Engineer
HCLTech
Noida
Verification Engineer 2
Qualcomm
I worked on verification for the Turing subsystem, where I verified multiple modules within the subsystem and also had the opportunity to work on formal verification
Verification Engineer
Incise Infotech Limited
Noida, Uttar Pradesh, India
Verified the DDR4 memory controller for the ODC project at Andes Technology, ensuring compliance with JEDEC standards and robust integration with system components. Developed and executed detailed test plans and directed/constraint-random test cases to validate read/write operations, initialization sequences, and timing parameters. Performed debug and root-cause analysis using simulation waveforms and logs to resolve functional issues in the memory subsystem.
Verification Engineer
NXP Semiconductors
Noida, Uttar Pradesh, India
Worked on Clock, Reset, and Power Management (CRPM) for Flexible SubSystem (FSS) and Common SubSystem (CoSS), focusing on low-power design and efficient system integration. Contributed to the development and validation of CRPM infrastructure, collaborating with architecture, RTL, and verification teams to implement power optimization techniques such as power gating, clock gating, and DVFS. Supported bring-up and debugging on pre-silicon platforms using simulation, emulation, and hardware prototypes.
Graduate Engineering Trainee
Synopsys Inc
Bengaluru, Karnataka, India
Successfully verified the ARCSync module, designed to accelerate AI workloads by enabling synchronization across multiple ARC processors. Developed and executed comprehensive test cases, achieving full functional and code coverage for the module. Verified all key features of ARCSync, including synchronization mechanisms and AI acceleration support, along with thorough validation of the Power Management Unit (PMU).
Trainee at Maven Silicon, Bangalore
Maven Silicon
Bengaluru, Karnataka, India
Completed Advance Design and Verification course. Hands on experience on 2 major projects: Router 1X3 packet design based protocol and Dual ported RAM(DPRAM) respectively.
Electronic Engineer
Truechip
Noida, Uttar Pradesh, India
Completed CEP VLSI course.
Education
ABES Engineering College
Electrical, Electronics and Communications Engineering
Ayush Pathak's Contact Information
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