Arish Sateesan

Assistant Professor @ Aalborg University

About

I am an Assistant Professor in Cybersecurity, and my research focuses on FPGA-based systems, embedded AI, and hardware security for high-speed edge networks. My research aims to build trustworthy and energy-efficient hardware platforms that enable real-time AI inference and security functions directly at the network edge. By co-designing algorithms and reconfigurable architectures, I address challenges in scalability, latency, and privacy across edge computing, cyber-physical systems, and next-generation communication networks. My work spans high-speed networking, resource-constrained embedded devices, and millimeter-wave systems, with validation on state-of-the-art FPGA platforms. I actively pursue interdisciplinary and industry collaborations to translate hardware innovation into resilient digital infrastructure.

Country

Denmark

City

Copenhagen

Industry

Research

Skill

Teaching Skills, AI hardware acceleration, Automated hardware generation, AI on resource-constrained hardware, mmWave Communication, Embedded AI, 6G, Network Security, Hardware Architecture, Electrical Engineering, Computer Architecture, Firmware, Sensors, Static Timing Analysis, Embedded Systems, Artificial Intelligence (AI), Machine Learning, Deep Learning, Electronic Engineering, Digital Designs

Experience

Assistant Professor

Aalborg University

2026-2 - Present · 8 mos

Copenhagen, Capital Region of Denmark, Denmark

Postdoctoral Researcher

RWTH Aachen University

2024-3 - 2025-11 · 1 yr 9 mos

Aachen, North Rhine-Westphalia, Germany

FPGA-accelerated, privacy-aware, mmWave communication systems Edge AI accelerators using quantized neural networks (QNNs) Real-time multi-modal sensor fusion on FPGA testbeds

Doctoral Researcher at COSIC, KU Leuven

KU Leuven

2019-4 - 2024-2 · 4 yrs 11 mos

Leuven, Flemish Region, Belgium

FPGA architectures for high-speed network security DDoS mitigation algorithms for Terabit Ethernet Privacy-preserving on-premise hardware security systems Probabilistic and approximate membership query data structures

Research Associate

Nanyang Technological University Singapore

2018-6 - 2019-4 · 11 mos

Singapore

Automated design synthesis for deep learning on FPGAs Resource-constrained AI optimization Hardware-software co-design for edge AI

Systems engineer

IBM

2016-1 - 2018-5 · 2 yrs 5 mos

Chennai Area, India

Business intelligence & data analytics solutions

Systems Engineer

G4 Matrix technologies

2011-5 - 2012-5 · 1 yr 1 mo

Trivandrum

ARM-FPGA systems for real-time image processing Hardware validation & system integration

Lecturer

CAPE

2010-1 - 2011-5 · 1 yr 5 mos

Kottayam

Undergraduate teaching Curriculum delivery, lab supervision & student evaluation

Education

KU Leuven

Electrical Engineering

2019-4 - 2024-1 · 4 yrs 10 mos

Doctoral researcher at KU Leuven in collaboration with ETH Zurich in a joint research project ESCALATE: My primary research area is FPGA design for network security. My work concentrates on the acceleration of large flow detection algorithms using configurable hardware. An algorithm-architecture co-design approach will be followed to develop novel algorithms and implementations for data flows that only exceed the allowed bandwidth to a limited extent. The goal is to integrate the configurable hardware in network devices and demonstrate efficient and effective protection against large flow network attacks.