ArchanaRaj Puttaraju

Graduate Service Assistant @ Arizona State University

About

Master’s student in Electrical Engineering at Arizona State University specializing in ASIC Physical Design, RTL Design, Timing Closure, Verification, and VLSI implementation across advanced technology nodes.Hands-on experience executing complete RTL-to-GDSII flows using Cadence Innovus and Synopsys tools, including floorplanning, placement, CTS, routing, ECO implementation, MCMM timing closure, STA, congestion analysis, IR-drop optimization, and signoff verification on 7nm/32nm/40nm technologies.Built and verified SystemVerilog RTL for pipelined processors, FIFOs, accelerators, arithmetic units, and memory-interface blocks with strong understanding of microarchitecture, cache systems, timing analysis, and SoC integration.Experienced with:• Physical Design: Floorplanning, Placement, CTS, Routing, ECO, PPA Optimization, DRC/LVS, EMIR, Congestion Analysis• RTL & Verification: SystemVerilog, Verilog, SVA, FIFO Design, CDC Awareness, Microarchitecture• Timing & Signoff: STA, MCMM Analysis, Setup/Hold Closure, PrimeTime, QoR Optimization• Tools: Cadence Innovus, Virtuoso, Spectre, PrimeTime, Fusion Compiler, Design Compiler, Calibre, ModelSim• Scripting: Tcl, Python, Perl, C/C++Delivered measurable improvements in WNS/TNS, routing congestion, clock skew, power, and timing closure through backend optimization and automation-driven design flows.Actively seeking Full-Time opportunities (2026) in:ASIC Physical Design | RTL Design | Verification | VLSI Design | Backend Design | ASIC Implementation | Timing Closure | SoC Design

Country

United States

City

Tempe

Industry

Semiconductors

Skill

ASIC Physical Design, Universal Verification Methodology (UVM), Signal Processing, Digital Signal Processing, K-Nearest Neighbors (KNN), Logistic Regression, RTL Coding, Python (Programming Language), ModelSim, FPGA, Machine Learning, HSPICE, Cadence Software, CMOS, Adder, RTL Design, SystemVerilog, Verilog, Static Timing Analysis, Clock Tree Synthesis

Experience

Graduate Service Assistant

Arizona State University

2025-8 - Present · 1 yr 2 mos

Tempe, Arizona, United States

Grader – EEE 334: Circuits II School of Electrical, Computer and Energy Engineering, Arizona State University Graded assignments and exams for EEE 334: Circuits II, a core Electrical Engineering course, under Prof. Jennifer Kitchen, Prof. Deliang Fan, and Prof. Marnie Wong. Assessed student work on op-amps, diodes, MOSFETs & BJTs, small-signal amplifiers, and introductory digital circuits. Strengthened expertise in circuit analysis, design, and evaluation of problem-solving methodologies.

Physical Design Intern

Skanray Technologies

2023-8 - 2023-12 · 5 mos

Mysore

Physical Design Intern — Skanray Technologies Ltd Aug 2023 – Dec 2023 • Implemented full ASIC backend flow for digital IP blocks (~100K standard cells) including floorplanning, placement, CTS, routing, and physical signoff • Closed setup and hold timing violations across multiple timing corners, improving TNS by ~25% during optimization cycles • Reduced clock skew below 120ps using useful-skew balancing, CTS optimization, and buffer insertion strategies • Performed DRC/LVS-clean verification and collaborated with RTL teams for ECO implementation and timing fixes • Executed congestion analysis, timing optimization, and PPA improvement using industry-standard Cadence/Synopsys flows • Contributed to timing closure and backend signoff for ASIC implementation workflows

Education

Arizona State University

Electrical Engineering

2024-8 - 2026-5 · 1 yr 10 mos

Coursework: Digital Systems and Circuits, Python, VLSI Design, Computer Architecture, Machine Learning Basics with Deployment to FPGAs, Digital Signal Processing, Fundamentals of Semiconductor Packaging, Embedded Machine Learning , Adv Semiconductor Packaging