Archana Raut

Archana Raut

Component Design Engineer

About

18yrs of experience in leading verification efforts across SOC, subsystem, IP level, delivered multiple successful products for Intel, LSI, Synopsis, Virage Logic, Ingot System, Alliance semiconductor . Key area of expertise: * Cache coherency validation of multi-core server processors and network processors ( Intel's server and client coherent fabric, ARM cache coherent network interconnect CCN512) * System memory controller ( DDR2/3, LPDDR/LPDDR2) * PCI-E, PCI/PCIX to PCI-E bridge * AXI, AHB, APB * In-field repair, power on repair and DFT verification of network processors * Hands on experience in verification environment development ( System verilog, VMM, OVM, UVM)

Country

India

City

Bengaluru

Industry

Semiconductors

Skill

Computer Architecture, Coverage Analysis, Functional Verification, ASIC, Application-Specific Integrated Circuits (ASIC), Verilog, Debugging, SoC, System on a Chip (SoC), SystemVerilog

Experience

Intel India Ltd

Component Design Engineer

Intel India Ltd

2014-11 - Present · 11 yrs 11 mos
LSI, an Avago Technologies Company

ASIC DvDs Engineer Senior

LSI, an Avago Technologies Company

LinkedIn
2010-12 - 2014-11 · 4 yrs
Synopsys Inc

R & D Eng-II

Synopsys Inc

LinkedIn
2010-8 - 2010-12 · 5 mos
Virage Logic

Sr. ASIC Engineer

Virage Logic

LinkedIn
2005-10 - 2010-7 · 4 yrs 10 mos
Alliance Semiconductor

ASIC Design Engineer

Alliance Semiconductor

LinkedIn
2004-8 - 2005-9 · 1 yr 2 mos

Education

Visvesvaraya National Institute of Technology

Visvesvaraya National Institute of Technology

LinkedIn

Electronics

2001 - 2003 · 2 yrs
Visvesvaraya National Institute of Technology

Visvesvaraya National Institute of Technology

LinkedIn

Archana Raut's Contact Information

Email

******@***.com

Phone

(**) *** ****

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