Anusha Naganur
Senior DFT Engineer @ Mirafra Technologies
About
TRAINED DFT ENGINEER DFT (Design For Testabilty) Domain - trained in DFT (Synopsys Tool) Scan insertion, scan compression, Boundary Scan (JTAG) and undergoing ATPG Tools used: Scan insertion: DFT compiler Scan compression: DFT complier Boundary Scan (JTAG) : BSD complier ATPG: Tetramax Simulation: VCS Training included projects w.r.t scan insertion, scan insertion with compression , boundary scan(JTAG), ATPG Pattern generation and Simulation along with analysis of DRC violations and fixing using Synopsys Tool
India
Bengaluru
Information Technology & Services
Gate Level Simulation, Automatic Test Pattern Generation (ATPG), English, Engineering, Project Management, Communication, Problem Solving, Management, DFT, Verilog, Scan Insertion, Joint Test Action Group (JTAG), Scan compression, OCC, Boundary Scan
Experience
Senior DFT Engineer
Mirafra Technologies
Bengaluru, Karnataka, India
DFT Engineer
Qualcomm
Bengaluru, Karnataka, India
Education
Visvesvaraya Technological University
Electrical and Electronics Engineering
Anusha Naganur's Contact Information
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