Anuj R.

- Exploration of architectural optimizations to GPU memory subsystem using cycle-accurate GPU simulators - Validating performance enhancements through specific directed tests on the in-house GPU models - Currently focusing on improvisations to the memory management unit and memory controller architecture to keep up with state-of-the-art stacked DDR memory

- Architecting and automating the integration of RISC-V ISA based open source processor (running primitive Linux) with multiple HLS generated accelerators - Developing test cases with accelerator specific custom instructions for verifying the integration across hardware and software layers - Architecture validation and deployment of the developed infrastructures as an open source resource

- Worked on full-stack integration of open-source RISC-V based rocket core (running primitive Linux) with an in-house accelerator in System Verilog - Hacked into and brought up Linux for RISC-V to accomodate accelerator extensions on rocket core - Understood and developed suitable modifications across hardware and software stack of the system for handling virtual memory

- Worked on RTL design of a low latency, deadlock free, scalable Network-on-chip (NoC) with wormhole routing using Chisel HDL, for interconnecting a multiprocessing fabric - Implemented the micro-architecture for a 6 stage out-of-order single issue pipelined processor that implements the RISC-V ISA with target-specific instruction support - Implemented a tightly coupled hw/sw codesign of a fabric of multiprocessor cores interconnected by a 32 node NoC with Microblaze soft cores running software programs for unfinished hardware modules, to emulate a runtime reconfigurable macro-dataflow hardware accelerator (CGRA) on 3 Virtex7 multiFGPA board - Developed front-end passes over Clang to transform programs written in C/C++ (with support for Intel's Concurrent Collections library) into a task based graphical intermediate representation - Currently contributing to the LLVM backend for a many-core target that takes static and dynamic task-based graphs of applications as input and automatically produces optimally parallelized machine code with target-specific instructions to manage memory and compute resources on the accelerator fabric - Designed a Hardware Random Number Generator in RTL for cryptography applications with verification & NIST quality testing - Analysed and compared the implementation details of low power design techniques for Systems-on-chip IPs

- Development of in-house CAD tools and checks for pre- and post-DFT RTL netlisting and physical designing (PD). - Generated regressions (test-cases) for the CAD tools with adequate coverage to detect specific design faults in the netlist - Worked closely with ASIC PD and DFT design teams for tool enhancement after diagnosing and identifying design issues

- Physical designing of a multi-million gate SoC in 16nm FINFET technology using IC compiler - Decided floor plan and performed cell placement, clock-tree synthesis and routing for several complex blocks - Carried out static timing analysis for setup/hold timing closure on all PVT corners at 1GHz - Signed off with ECOs for signal integrity using PrimeTime, IR drop analysis using RedHawk and DRCs using Calibre

- Assisted in the development and testing of a condition-based monitoring system for inaccessible gas pipelines using TelosB Wireless Sensor Network motes - Implemented an adhoc network based energy-efficient hierarchial protocol for data gathering and relaying

- Design of hotwell and deaerator water-level control system in the secondary heat transfer cycle of the nuclear reactor - Carried out mathematical modeling and stability analysis for 2 prospective control system models - Simulated the models with real input triggers using Simulink and graphically compared their stability