Anuj Shah

Anuj Shah

GPU Physical Design PPA Engineer @ Apple

About

Graduated from Arizona State University with specialization in Electronics and Mixed signal circuit design. Currently working at Apple.

Country

United States

City

Austin

Industry

Semiconductors

Skill

-

Experience

Apple

GPU Physical Design PPA Engineer

Apple

LinkedIn
2021-11 - Present · 4 yrs 11 mos

Austin, Texas, United States

Cadence

Product Engineer

Cadence

LinkedIn
2021-4 - 2021-10 · 7 mos

Austin, Texas, United States

• Involved in designing next generation capabilities of power estimation/rail analysis tool to accommodate the ever-increasing complexities of chip design • Worked on developing new IR Aware Placement Flow to reduce IR Drop using Innovus • Worked with R&Ds and drove product development by exploring the possible algorithms and methodologies • Defined new technical specs and validated the new features

Cadence

Application Engineer

Cadence

LinkedIn
2020-3 - 2021-4 · 1 yr 2 mos

Austin, Texas Area

• Understood problem statements from transistor level and came up with innovative solutions • Simulated macros using Spectre models in Virtuoso and compared results with Voltus • Experience in running IR (static), IVD, Power EM, Signal EM and analyzed results

Cirrus Logic

Physical Design Engineer

Cirrus Logic

LinkedIn
2018-7 - 2020-3 · 1 yr 9 mos

Austin, Texas Area

• Responsible for running EM and IR Drop analysis using Voltus on Cirrus Logic’s next generation audio products • Used Voltus and Prime Power for average, vectorbased, vectorless and inrush power analysis • Closely worked with P&R engineers and provided feedback to improve power grid/reduce IR drop • Designed decap cells which improved cap density by 150% & reduced leakage/fF by 28% compared to foundry decap cells • Designed Level Shifters, delay cells and I2C deglitch blocks and ran EM, IR drop, AMS, SOA checks, transient analysis on extracted netlist using Cadence Virtuoso

Cirrus Logic

IP Design Engineer

Cirrus Logic

LinkedIn
2015-6 - 2018-7 · 3 yrs 2 mos

Austin, Texas Area

• Involved in re-package and distribution of 3rd party IP as well as development, characterization, view-generation, maintenance, qualification and distribution of in-house IP including standard cells and memories • Responsible for IO development (custom macro transistor level design) like custom GPIO, power, ground pads, I2C, SoundWire PHY interface • Worked with cross functional teams to gather/define/implement specs • Transistor level implementation of the block using CMOS/Domino/Cell-Based styles • Responsible for running layout extracted simulation (PEX) and provided additional views like Verilog, abstract, LEF, timing models like CCS, ECSM, NLDM, AOCV, OCV (for STA) etc. • Closely worked with Product Test Engineers and Validation Engineers to characterize/review Silicon data • Used wide range of analog and digital design tools as well as script development for automation purpose • Used Perforce as a revision control tool to manage data

Education

Arizona State University

Arizona State University

LinkedIn

Electronics and Mixed Signal Circuit Design

2013 - 2015 · 2 yrs
L.D. College of Engineering

L.D. College of Engineering

LinkedIn

Electrical, Electronics and Communications Engineering

2008 - 2012 · 4 yrs

Anuj Shah's Contact Information

Email

******@***.com

Phone

(**) *** ****

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