Antony Peeris A

DFT Engineer ;2.5 Year Experience ; 1. Experience in DFT validation and automatic Test pattern generation ,scan insertion and coverage analysis. 2. Generation and Validation of Functional Test Patterns for multimillion gate complex System on Chips. 3. GLS,PAGLS simulations with timing and no timing 4. Experience in debugging the ATE failing test patterns. Skills: Coverage analysis for stuck at and transition patterns ,knowledge on RC DFT scan insertion, pattern compression,JTAG,P1500 Good in developing Assembly level test suites for ARM7, CortexR4 based System on Chip designs. Understanding of end to end standard ASIC design flows including RTL, synthesis Timings , DFT methodologies & tools, ATE testing at wafer level and package parts

Total of 1 year 3 months with Wipro Technologies Bangalore – presently working as Project Engineer. Client (Texas Instruments) Experience in Gate Level Simulations, Generation and Validation of Functional Test Patterns(BIST,MBIST) for multi million gate complex System on Chips.  Responsible for driving the team to generate and handoff the functional test patterns for the validation of silicon samples on Automotive Test Equipment (ATE).  Experience in debugging the ATE failing test patterns Good in developing Assembly level test suites for ARM7, CortexR4, and CortexM3 based System on Chip designs Understanding of end to end standard ASIC design flows including RTL, Verilog simulators, Synthesis,STA, basic DFT methodologies & tools, BIST and MBIST Patterns generation,ATE testing at wafer level and package parts.