Lakshmi Anirudh Ghantasala

Developing the hardware for the future of intelligent compute

Developing the hardware for the future of intelligent compute

Post-Internship I have resumed my PhD work. I am designing methods to improve the decades-old problem of protein folding with probabilistic computing architectures.

My experience largely deals with hardware architectures for physics-based problem solvers, from microcontroller circuits to FPGA design. Through this work, I've become familiarized with various types of neural networks as well as implementing them in a broad range of settings, including MATLAB, python, C++, and in an FPGA. I've extensively worked with AWS EC2 and Google Collaboratory to expedite our processes. • Designed microcontroller architecture for p-bits [published] (2016) • Co-built synchronous FPGA architecture for expedited p-circuit execution [published] (2017) • Co-built asynchronous FPGA architecture for cloud-based p-circuit operation [published] (2018) • Built headline website (with JavaScript simulator) for p-bit research at Purdue at www.purdue.edu/p-bit (2019) • Developed a comprehensive python p-bit package with GPU/FPGA integration to be published on Github (2019) • Carried out implementation and extensive benchmarking of various ML algorithms in MATLAB and Python not limited to SVMs, CNNs, RNNs, and LSTMS (2018-2021)

While many are focused on making the transistor smaller and more efficient, the contacts through which transistors communicate with one another are just as important. Under Prof. Zhihong Chen, I researched optimization of copper contacts in nanodevices. Furthermore, I took part in exfoliating graphene from carbon powder, and tungsten diselenide, whose electron spin properties are of great interest. I worked in the cleanrooms at the Birck Nanotechnology Center for a year characterizing graphene and tungsten diselenide flakes, and synthesizing graphene transistors. Special software allowed me to layout contacts around graphene flakes on a silicon chip, while the actual lithography was done by a lab technician.

• Accelerated edge AI models for in-car driver recognition using a custom, low-powered ASIC. Combined a comprehensive set of models that could detect driver activity, seatbelt presence, eye movements, and other tracked quantities into a single, low-power solution while maintaining accuracy going from single-precision to 8-bit inference. • Developed a C++ QT application for in-cabin passenger detection and live monitoring for forgotten items as passengers get in and leave a car. Solution integrates with an ML library backend to provide real-time feedback. • Optimized production grade facial recognition model using detection thresholding, edge case performance metrics, ROC curves • Built automobile driver facial recognition dataset

Became proficient with C++ development in a purely UNIX (bash) environment. IT Seers is a consulting firm in Bangalore India, which serves the IT needs of clients. My duties here entailed developing C++ code which would enhance the accuracy of Optical Character Recognition software by training the default OpenCV recognition software with handwritten images. • Improved upon standard OCR (optical character recognition) ML OpenCV code • Trained default OpenCV recognition network to better recognize cursive handwriting with cursive image training sets

My introduction to graphene transistors was here. Here, I had a crash course in the steps used to create a graphene transistor. By the latter part of the summer, I aided a PhD student in testing for an optimal sequence of operations to synthesize a graphene transistor. I took part in and observed a wide variety of techniques employed today in transistor fabrication and research, including but not limited to : - Lithography - Application of Masks - Electron Beam Melting (EBM) evaporation - Scanning Electron Microscopy (SEM) - Transmission Electron Microscopy (TEM) - Atomic Force Microscopy (AFM) - Raman Spectroscopy - Physical Vapor Deposition (PVD) - Chemical Vapor Deposition (CVD) I explain a summary of these techniques, as well as a summary of my entire work at IISC, in the attached informal write up.

The official duty of a Test Lab Technician is to run quality tests on various equipment engineered by Stryker, including surgical drill tests, surgery headlight tests, and various proprietary Stryker devices. While I started with these intentions, i quickly grew frustrated with how slow certain testing procedures were. One of these tests required users to scan a list of results to separate those results that fell in a certain range. This was a mundane task which could easily be automated. I learned visual basic and automated the process within a few days. The results were noted by the manager, who put me in touch with the only programmer for the test lab. My automation was then put into effect in the test lab officially. Key points: - Learned Visual Basic on the job, and implemented it in a company setting - Programmed data-acquisition macros in visual basic to facilitate automated testing - Coded alongside the lead programmer of the test lab within 1 month of joining - Ran quality tests, including autoclave surgical drill wash testing and surgical headlight duration testing

My PhD is in extending probabilistic computing to beyond-ising applications, notably to feed-forward machine learning.

My coursework has targeted solid state transistor physics and computer algorithms, while my research specialization within EE is in spintronics and neural networks.

I completed my undergraduate studies in Electrical Engineering, while also taking most of the computer science courses required for Computer Engineering. In addition, I completed a minor in Biology and a minor in English.

Begins in the spring of 2020 and continue for a few years, with a focus on stochastic neural networks and FPGA/microcontroller development.