Andrey Shevchenko

- 5G NR ORAN RU and DU architecture design, RU development technical leading - Modem hardware architecture design for 5G NR gNB and FWA wireless systems - Algorithm design of a receiver for SC-FDE and OFDM systems - Low-latency system design and hardware implementation, - Design and implementation of MAC for the proprietary multi-Gigabit communication systems - Layer 2 network switch design and implementation for P2P and P2MP commuications - Design of hardware accelerators for 5G NR L1 Offloading

● High speed V-band and E-band radio relay systems development, ● Synchronization, acquisition and tracking algorithms synthesis for SC-FDE wireless systems ● Digital compensation of analog RF front-end impairments (CFO, Phase Noise, IQ-imbalance, DC offset) research and implementation ● MAC algorithm development (ARQ, PLA, Flow Control) ● DSP algorithms hardware implementation (Verilog)

● SoC IP blocks development for UWB communications ● FPGA-based implementation and components verification ● FEC algorithms research for IEEE 802.11ad

● R&D of FEC algorithms for wireless outdoor communications (Conv. Codes, LDPC, RS), ● OFDM and SC-FDE systems link level simulation ● Hardware implementation of OFDM and SC-FDE baseband algorithms for wireless communications system ● Channel model development for outdoor wideband systems