andrew webb

digital designer principal

About

I have 20+ years of experience as a digital designer (both custom and RTL-based). Have worked on microcontrollers, video hardware accellerators, and most recently on mixed-signal CSP (RX/TX and control sections for GSM and WCDMA chips) and PMU (Power Management Unit) chips (have digital, will travel). Experience spans just about the entire life cycle of an integrated circuit (definition, RTL coding or schematic capture, synthesis, functional and circuit verification, test vector generation and debug). Specialties: RTL coding, functional verification/testbench creation, design testability

Country

united states

City

new york

Industry

semiconductors

Skill

asic, soc, static timing analysis, integrated circuit design, rtl design, dft, cmos, eda, functional verification, vlsi, verilog, tcl, semiconductors, hardware architecture, low power design, circuit design, cadence virtuoso, timing closure, schematic capture, semiconductor industry, processors, modelsim, hardware, vhdl, debugging, logic synthesis, cadence, public speaking, communication, leadership

Experience

dmts

lsi/agere/lucent/at&t bell labs

1993-1 - 2007-1 · 14 yrs 1 mo

designer

rca semiconductor

1986-1 - 1990-1 · 4 yrs 1 mo

mts - digital design engineer

intel corporation

1990-1 - 1993-1 · 3 yrs 1 mo

Worked in Plainsboro, NJ doing Video processor (DVI, a technology purchased by Intel from RCA's Sarnoff Labs) doing custom digital control and datapath design

senior specialist ic design

intel corporation

2011-2 - 2012-9 · 1 yr 8 mos

Working in all phases of IC digital design (RTL design, synthesis, verification, etc.) on devices for the mobile/cellular market

design engineer

infineon technologies

2008-10 - 2011-1 · 2 yrs 4 mos

Currently working on the digital portions of mixed-signal CSP and PMU chips used in mobile phones (design, coding and verification) and top-level SOC functional verification

digital designer principal

intersil

2012-10 - Present · 14 yrs

digital design engineer at intersil

intersil

2012-10 - Present · 14 yrs

Handle all phases of digital design (RTL design, verification, testability) in support of mixed-signal Power Management devices

Education

hamilton west - watson high school

rutgers university

computer engineering

rutgers university

engineering

rutgers university

electrical engineering

1982-1 - 1995-1 · 13 yrs 1 mo

Graduated with BSEE in 1986, took a couple of years off and then went back at night to get MSEE in 1995 Activities and Societies: Member of Tau Beta Pi and Eta Kappa Nu