Anand Shanmugam S

Anand Shanmugam S

Manager - Hardware - Power Architecture & ASIC @ NVIDIA

About

10+ Experience in VLSI Hardware Design. Areas of Expertise: * LowPower Architecture, RTL Design, Methodologies & Verification * LowPower Techniques & Features, Innovation * UPF Standards * Verification Methodologies - Static & Dynamic RTL/Netlist Verification * SOC/Full-chip Architecture * SOC/Full-chip RTL Design * SOC/Full-chip Verification * Silicon Bringup/Post-Silicon Debug * Complex Problem Solving

Country

India

City

Bengaluru

Industry

Computer Hardware

Skill

Low-Power Architecture, Design & Verification, Project Management, Engineering, ASIC, SOC, Architecture, Research, Analytical Skills, Verilog, VHDL, Perl, C, C++, Leadership, Communication, Training, Problem Solving, Presentations, Management, English

Experience

NVIDIA

Manager - Hardware - Power Architecture & ASIC

NVIDIA

LinkedIn
2020-6 - Present · 6 yrs 4 mos

Bengaluru, Karnataka, India

Managing & Technically leading a team of Hardware engineers working on Low Power. * LowPower Features - Architecture/RTL Design/Verif/Silicon Bringup: Spec to Silicon (End-to-End LowPower Architecture, Design, Verification & Silicon Bringup) * Power Methodologies: Power Intent, Power Structure Insertion, Static & Dynamic Verification * Power DV Methodologies: Verification Methodologies for Low Power * Process Improvements: Development of new flows for optimized delivery with High Quality, Efficiency & Timely completion.

NVIDIA

Senior Engineer - Hardware - LowPower

NVIDIA

LinkedIn
2014-7 - 2020-6 · 6 yrs

Bengaluru, Karnataka, India

LowPower Architecture, RTL Design, Verification & Silicon Bringup. LowPower Project Lead: Technical Project Lead for teams of hardware engineers working on Lowpower Architecture, RTL Design, Methodologies, Verification & Bringup. Mentor engineers for successful delivery of LowPower Projects.

NVIDIA

ASIC Design Engineer

NVIDIA

LinkedIn
2011-7 - 2014-6 · 3 yrs

Bengaluru, Karnataka, India

LowPower RTL Design & Verification, SOC/Full-chip RTL & Gate-Level Verification of GPUs

Education

Indian Institute of Technology, Madras

Indian Institute of Technology, Madras

LinkedIn

VLSI Design

2010 - 2011 · 1 yr
Anna University Chennai

Anna University Chennai

LinkedIn

Electronics & Communication Engineering

2007 - 2011 · 4 yrs
SRDF Vivekananda Vidyalaya, Chennai

SRDF Vivekananda Vidyalaya, Chennai

LinkedIn
2005 - 2007 · 2 yrs

Anand Shanmugam S's Contact Information

Email

******@***.com

Phone

(**) *** ****

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