Anahita Shayesteh

Principal Deep Learning Architect and Senior Manager @ NVIDIA

About

--Computer and system architect with Ph.D. in Computer Science and 16 years of diverse industry experience spanning CPU, GPU and ML accelerator architecture, interconnection networks, caches, storage architecture and software/hardware co-design. --In depth knowledge of CPU arch/micro-arch. Strong knowledge of cache hierarchy, coherence protocols and on-die interconnects, GPGPU hardware, ML specific hardware and parallel programming paradigms. --Experienced in system performance analysis, modeling and hardware/software tuning and optimization. Workload characterization and optimization. Simulator development and analysis. (Mostly C/C++ and Python) --Solid understanding of Deep learning fundamentals, familiar with state of the art ML models (LLMs, Rec Sys, etc). Knowledgeable on parallelization paradigms and performance analysis of large models at scale. --Knowledgeable in datacenter applications and frameworks. Familiar with memory/storage subsystems, new storage technologies and the associated characteristics of datacenter applications.

Country

United States

City

Los Altos

Industry

Computer Hardware

Skill

Large Language Models (LLM), Deep Learning, Computer Architecture, Simulations, Processors, Algorithms, GPGPU, High Performance Computing, Microprocessors, Microarchitecture, Parallel Computing, Parallel Programming, Optimization, GPU, C++

Experience

Principal Deep Learning Architect and Senior Manager

NVIDIA

2023-11 - Present · 2 yrs 11 mos

Santa Clara, California, United States

Principal Systems Architect, HW/SW Co-design Lead

Luminous Computing

2021-10 - 2023-10 · 2 yrs 1 mo

Mountain View, California, United States

Led and directed performance modeling, workload characterization, and hardware/software co-design efforts at Luminous Computing. Collaborated closely with architecture, compiler, and machine learning teams to define system requirements and identify bottlenecks in our architecture. Proposed new optimization features. Created analytical (roof-line based) performance models for various ML workloads at scale, including Large Language Models, Recommender Systems, and Stable Diffusion. These models were utilized to set the memory and compute targets to define a balanced and competitive system.

Sr. Staff Systems Engineer

Samsung Electronics

2014-3 - 2020-2 · 6 yrs

San Jose

 Key contributor involved in definition, architecture and POC development of Samsung Smart SSD. Researched opportunities for “Near Storage Compute” in different datacenter applications. Conducted detailed performance analysis of offloading kernels in a columnar datastore.  Evaluated and optimized datacenter frameworks and applications for new storage technologies. Conducted detailed study of NVMe and NVMe-oF and opportunities in data centers.

Research Scientist / Hardware Engineer

Intel

2006-7 - 2014-2 · 7 yrs 8 mos

Researched new features in CPU/GPU architecture, Cache hierarchy and on die interconnect. Modeled new features in simulators (functional and cycle accurate) and analyzed performance and trade-offs.