Ambarish J

Senior Engineer @ Wipro

About

~One of a kind Engineer~ The devices around my home (like the TV) triggered my curiosity to find out it's internal components. (Ended up being notorious for detaching the front of the CRT monitor - repeatedly...) Our first washing machine paved my mind into automation (still gets me everytime I see it work...) creating a zeal in inventing automatic devices, setting it in motion and enjoying the events that unfold. I knew... Anything is possible. Engineering was not 'AN' option, it was the 'ONLY' option. Nothing else intrigued me more. Instrumentation was my field. Never had any second thoughts. Automation in industries provoked PLC and SCADA training and the unquenchable thirst for inventing devices prompted me to pursue Masters in Technology in Electronics Design Technology (EDT). Love Hardware Engineering (Digital Design) and Product Development Worked as an intern in NXP Semiconductors from 5th August 2019 to 3rd July 2020. It was my first work experience. I will never forget the people I befriended, the lessons I learnt and the memories I made both at the professional and personal front. Responsibilities included developing standard cells to improve design PPA, reliability simulation to compensate for aged-degradation, automation of library characterization and more. Other Interesting Areas: Entrepreneurship and Semiconductors

Country

City

India

Industry

Semiconductors

Skill

Analog Characterization, Analog Circuit Design, Macro cell characterization, Synopsys SiliconSmart, Cadence Liberate, Problem Solving, Digital Electronics, Cadence Virtuoso Layout Editor, Circuit, Cadence SKILL programming, Standard Cell, Library Characterization, Python (Programming Language), Engineering, Entrepreneurship, Reliability, Verilog, Microsoft Office, C (Programming Language), Microsoft Excel

Experience

Senior Engineer

Wipro

2024-3 - Present · 2 yrs 7 mos

Bengaluru, Karnataka, India

Memory Characterization at Intel (client) March '25 - Present Analog Characterization at Micron (client) April '24 - Feb '25

Product Engineer II

Cadence

2022-9 - 2024-1 · 1 yr 5 mos

Bengaluru, Karnataka, India

VLSI CAD Engineer

Intel Corporation

2022-7 - 2022-8 · 2 mos

Bengaluru, Karnataka, India

Memory Layout Engineer (ICE)

Intel Corporation

2021-4 - 2022-6 · 1 yr 3 mos

Bengaluru, Karnataka, India

Responsible for developing Memory Layout IPs and validation of Physical Design checks (such as LVS, DRC, Density, etc.) and Reliability Verification (such as EM, IR drops, etc.) through regression across multiple technology nodes (22nm and 10nm). • Developed Memory layout IP for 10nm SoC and ran Physical Design verification for the same through bundle flow. • Developed a Python automation script from scratch to run validation checks such as LVS and DRC through various flows.

Digital Design Engineer (Standard Cell - Library and Layout characterization)

NXP Semiconductors

2019-8 - 2020-6 · 11 mos

Bengaluru Area, India

Intern at NXP Semiconductors. Responsibilities included developing standard cells to improve design PPA, reliability simulation to compensate for aged-degradation, automation of library characterization and more. Created an automation script using Python to generate an age-degraded Netlist and Liberty model for Standard Cells of a given nanometer technology. Got accustomed with Spectre, Mica and SPICE models. Fluent in Library development, characterization and generating Liberty Models with SiliconSmart. Well-versed with Cadence Virtuoso. Thorough understanding in Python Automation Scripting.