Alexandros Papakonstantinou

Alexandros Papakonstantinou

GPU Compiler Engineer @ Qualcomm

About

Computer Architect with experience in the design and development of GPUs and Multicore Accelerators as well as compiler design for heterogeneous architectures.

Country

United States

City

San Francisco Bay Area

Industry

Computer Software

Skill

Parallel Algorithms, SIMD, Performance Analysis, Computer Architecture, FPGA, Compilers, Hardware Design, Computer Engineering, Microarchitecture, VHDL, ModelSim, Verilog, VLSI, TCL, C, ASIC, C++, Assembly, Embedded Systems, Simulation

Experience

Qualcomm

GPU Compiler Engineer

Qualcomm

LinkedIn
2025 - Present · 1 yr

Santa Clara, California, United States

Lemurian Labs

Principal Compiler Engineer

Lemurian Labs

LinkedIn
2024-3 - 2025

Santa Clara, California, United States

Designing compilers for enabling portable performance of AI models on heterogeneous systems at scale.

Intel

Compiler Engineer

Intel

LinkedIn
2019-10 - 2024-3 · 4 yrs 6 mos

San Francisco Bay Area

Technical Lead in the P4 compiler team for Tofino high-speed networking devices.

Samsung Electronics

Senior Staff Engineer

Samsung Electronics

LinkedIn
2018-10 - 2019-10 · 1 yr 1 mo

San Jose, CA

Lead in the architecture team of Samsung's mobile GPU.

NVIDIA

Sr. GPU Architect

NVIDIA

LinkedIn
2012-7 - 2018-9 · 6 yrs 3 mos

Santa Clara, CA

Designed ML and HPC features for 5 generations of Nvidia GPU Streaming Multiprocessors (SMs).

University of Illinois Urbana-Champaign

Research and Teaching Assistant

University of Illinois Urbana-Champaign

LinkedIn
2006-1 - 2012-7 · 6 yrs 7 mos

Part-time employment at the University of Illinois, Urbana-Champaign during graduate studies toward the PhD. Research on: - High performance computing - Multicore architectures for parallel applications - FPGAs & GPU & CPU heterogeneous computing - High Level Synthesis and Compiler tool design - System on Chip & Embedded systems - Interconnection architectures, study of Network on Chip schemes

Intel Labs

Research Intern

Intel Labs

LinkedIn
2011-10 - 2012-1 · 4 mos

San Francisco Bay Area

Graduate Intern Technical in Microarchitecture Research Lab, Intel Labs. Research on fast exploration of alternative multicore architectures through automated hardware design based on high-level language transformations and high-level synthesis techniques.

AMD

CoOp Engineer

AMD

LinkedIn
2007-5 - 2007-8 · 4 mos

Austin, Texas

- Mobile x86 Processor Design Verification

Atmel Corporation

Senior ASIC Engineer

Atmel Corporation

LinkedIn
2004-2 - 2005-12 · 1 yr 11 mos

Patras, Greece

Infineon Technologies

Senior Design Engineer

Infineon Technologies

LinkedIn
2000-10 - 2003-12 · 3 yrs 3 mos

Bristol, United Kingdom

- Floating Point Unit study and design - Tricore 2 RTL Design - Tricore 2 Integer Pipeline owner - Tricore 2 LD/ST Pipeline Designer - Synthesis Flow owner - Place & Route Flow contributor

Education

University of Illinois Urbana-Champaign

University of Illinois Urbana-Champaign

LinkedIn

Computer Engineering

2006 - 2011 · 5 yrs
Imperial College London

Imperial College London

LinkedIn

Analogue and Digital IC design

1999 - 2000 · 1 yr
University of Patras

University of Patras

LinkedIn

Electrical & Computer Engineering

1994 - 1999 · 5 yrs

Alexandros Papakonstantinou's Contact Information

Email

******@***.com

Phone

(**) *** ****

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