Alexander Rumyantsev

Alexander Rumyantsev

Senior Design Engineer @ YADRO Microprocessors

Country

Russia

City

Moscow

Industry

Think Tanks

Skill

Verilog, SystemVerilog, SoC, RTL Design, PCIe, NCSim, ModelSim, Linux, Electronics, Testing, ARM, AXI, MMU, Synopsys Design Compiler, ASIC, Clock Domain Crossing, perl scripting

Experience

YADRO Microprocessors

Senior Design Engineer

YADRO Microprocessors

LinkedIn
2021-6 - Present · 5 yrs 3 mos

Москва, Москва, Россия

Baikal Electronics

Leading Design Engineer

Baikal Electronics

LinkedIn
2013-1 - 2021-5 · 8 yrs 5 mos

Moscow

Baikal-T1, Baikal-M, Baikal-S projects - Architecture of PCIe subsystem. - Configuration of Synopsys PCIe RC IP. - Integration PCIe controller and 10g PHY. - Writing SDC for PCIe subsystem - Trial logical synthesis - DFT insertion - CDC analysis - Integration PCIe subsystem in AXI fabric. - Debugging PCIe subsystem, LTSSM analysis - Writing UVM tests in an ready-made environment - SpyGlass tool linting analysis - Configuration and integration memories for the project. Writing the system to automatically generate, instantiate and simulate memories for the project. (using perl lang.) - Base knowledge of UPF concept (implementation MALI GPU IP Power Domains in conjunction with back-end team) - Integration 4K decoder IP in the project.

JSC NICEVT

Design Engineer

JSC NICEVT

2007-8 - 2012-12 · 5 yrs 5 mos

Moscow

Router Project - group operation subnet RTL designing - PCIe EP IP integration J7 CPU project - MMU architecture - MMU RTL designing

Education

National Research University of Electronic Technology (MIET)

National Research University of Electronic Technology (MIET)

LinkedIn

Микроэлектроника

2000 - 2006 · 6 yrs
National Research University of Electronic Technology (MIET)

National Research University of Electronic Technology (MIET)

LinkedIn

Alexander Rumyantsev's Contact Information

Email

******@***.com

Phone

(**) *** ****

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