Akshay Anup Vartak
ASIC Design Verification Engineer @ Google
About
I am currently working at Google in the TPU DV team. Briefly worked as a Design Verification-ICT3 Engineer in the Wireless SoC team at Apple. Worked on verifying CPU subsytem and Power manager. For almost 5 years, I worked at Intel as a SoC Logic Design Engineer specifically doing SoC verification of Power Management Controller. I graduated from the University of Southern California majoring in Computer Engineering
United States
San Jose
Semiconductors
Design verification, Universal Verification Methodology (UVM), System on a Chip (SoC), Verilog, SystemVerilog, RTL Design, Hardware Architecture, Field-Programmable Gate Arrays (FPGA), Very-Large-Scale Integration (VLSI), Application-Specific Integrated Circuits (ASIC), Machine Learning, Python, C++, VHDL, Matlab, Computer Hardware, Microsoft Office, C, Microsoft PowerPoint, Microsoft Excel
Experience
ASIC Design Verification Engineer
Sunnyvale, CA
Wireless SoC Design Verification Engineer
Apple
Sunnyvale, CA
SoC Logic Design Engineer
Intel
Santa Clara, California, United States
Integration and Verification of Power Management Controller (PMC) IP at SoC level. Platform Control Hub SoC Verification IP Security Client Product Group
Graduate Technical Intern
Intel
Folsom, California
SoC level Integration and Verification of Intel Platform Control Hub Design in Simulation based Environment.
Education
University of Southern California
Computer Engineering
Coursework : EE 457- Computer Systems Organization EE 560 -Digital System Design INF 552 - Machine Learning for Data Informatics EE 577A- VLSI System Design EE 576 - Integrated Memory Devices and Technology EE 590- Directed Research under Prof. Alice Parker
Vellore Institute of Technology
Electrical, Electronics and Communications Engineering
Akshay Anup Vartak's Contact Information
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