Akshay Joshi

Physical Design Engineer @ Apple

About

I am a currently working as an intern in GPU design team at Apple. I am pursuing my Masters in Computer Engineering from University of California San Diego. My fields of interest are RTL Design, Computer Architecture and front end validation. Previously, I have worked at Intel for more than 3 years on Xeon server projects. I signed off formal verification and back-end power checks.

Country

United States

City

Austin

Industry

Semiconductors

Skill

SystemVerilog, Synopsys VCLP, Computer Architecture, RTL Design, Formal Verification, Universal Verification Methodology (UVM), C++

Experience

Physical Design Engineer

Apple

2023-2 - Present · 3 yrs 8 mos

Austin, Texas, United States

GPU Design Intern

Apple

2022-6 - 2023-4 · 11 mos

Austin, Texas, United States

I am working as GPU intern with the following duties- - Resolve design and flow issues related to physical design, identify solution and help convergence. - Write TCL or Perl coding to improve efficiency of the implementation - Analyse and make tradeoffs, balancing power, performance and area for the design - Help develop floorplan, placement, clocking and routing QOR improvement methodology - Contribute to improve sigEM, crosstalk, LEQ/PWRV and post-PNR convergence cycle

SoC Design Engineer

Intel

2018-6 - 2021-9 · 3 yrs 4 mos

I was part of the Xeon Server back-end design team and I worked on signing off Formal Equivalence Verification (FEV) and power consistency checks for physical design of SoC for multiple projects. Cadence Conformal LEC and Synopsys VCLP tools were used for these applications.

Education

Indian Institute of Technology, Indore

Electrical and Electronics Engineering

2014-7 - 2018-5 · 3 yrs 11 mos

B.TECH. PROJECT: Title: Developing a book reading system for blind people by means of an android app Domain: Digital Signal Processing (Project Instructor: Dr. Vivek Kanhangad) Description: The project was to develop an algorithm which enables capturing an image of written text, converts it into audio output and provides guidance to the user while capturing the image using Matlab as the programming interface.

UC San Diego Jacobs School of Engineering

Computer Engineering

2021-9 - Present · 5 yrs 1 mo

M.S. PROJECT: Title: RTL design of SHA256 cryptographic algorithm for bitcoin hashing Description: SHA256 cryptographic algorithm was implemented using SystemVerilog. A message of up to 2 64 bits is taken as the input and the code generates eight hash values as the output. The algorithm is used for bitcoin hashing. Title: UVM testbench for testing RTL for SHA256 cryptographic algorithm Description: UVM testbench was implemented using SystemVerilog to test the RTL written in the previous project. Title: RTL design for 1-D Vector Processor based Architecture Description: Dual core architecture was implemented with optimizations like clock gating, normalizations, pipeline etc. Title: Implementation of code for Branch Predictor and Cache Description: This project was part of Computer Architecture class where Branch Predictor beating a given accuracy and 2-level cache hierarchy was implemented in C.