adi yacobson

senior vlsi backend cad engineer

About

VLSI Engineer at Marvell (Backend/Frontend)

Country

israel

City

israel

Industry

semiconductors

Skill

verilog, soc, asic, ic, static timing analysis, semiconductors, low power design, eda, mixed signal, logic synthesis, debugging, logic design, systemverilog, upf, cpf, vlsi, tcl, perl

Experience

backend cad

ben gurion university of the negev

2007-1 - 2007-3 · 3 mos

Implementing backend flow for VLSI imaging lab as a 2nd degree student final project

backend student

intel corporation

2006-2 - 2006-12 · 11 mos

senior backend cad engineer and low power static checks verificator

marvell semiconductor

2007-3 - 2013-12 · 6 yrs 10 mos

* Defined the methodology and implemented CPF based Backend low power static verification * flow including results analysis and APR ECO generation * Performed the low power static verification for a number of complex SoC chips * Physical implementation from RTL to GDSII including Floorplan, Placement, CTS routing & * Physical verification * Designed and implemented synthesis flow * Supported & enhanced the synthesis, APR & STA flows in terms of adding features, * debugging crashes & user support * Performed various backend interdisciplinary explorations * Written various automation scripts for deparment efficient workflow

senior vlsi backend cad engineer

intel corporation

2015-8 - Present · 11 yrs 2 mos

vlsi engineer

marvell israel ltd.

2014-1 - 2015-7 · 1 yr 7 mos

* Integration of RTL macros into SoC top level environment * Synthesis of logic blocks using Design Compiler * Leading Low Power Backend implementation flow methodology using UPF & CPF including * support to users * Writing complex UPFs including their verification in DC & ICC * Consultation for low power aware RTL methodology which will be “Backend friendly”