Adarsh Tripathi
Senior DFT Engineer @ Texas Instruments
India
Bengaluru
Professional Training & Coaching
DFT, SoC ATPG, SoC DFTlint, Cadence Modus, Jasper Gold, Pattern Simulation , Cadence Xcelium, SDF Simulation, Joint Test Action Group (JTAG), IO Parametric Tests, Static Timing Analysis, Digital Circuit Design, Ferroelectric Tunnel Junctions, Ferroelectrics, Linux Operating System, Python (Programming Language), Xcircuit, MATLAB, LaTeX, LTSpice
Experience
Senior DFT Engineer
Texas Instruments
Bengaluru
DFT Engineer
Texas Instruments
Bengaluru
Intern
AMD
Bengaluru, Karnataka, India
Placement Coordinator
Career Development & Placement Cell, IIT Ropar
Education
Indian Institute of Technology, Ropar
Microelectronics and VLSI Design
Shri G S Institute of Technology & Science
Electronics Telecommunication Engineering
Adarsh Tripathi's Contact Information
Phone
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