adam vishinsky

Developed a new topology for a rotational Hall sensor for automotive applications in 0.18 μm CMOS/LDMOS. Designed a low-noise Analog-Front-End and developed novel DSP CORDIC algorithms

* Tasked with the design of a 18 * 34 GHz clock distribution system in a CMOS 14 nm fin technology. Developed clock distribution system consisting of buffers, multiplexers, transmission lines and couplers. Reduced the jitter and improved the amplitude levels. Reviewed and redesigned a 18 * 34 GHz frequency divider by 2, 4, 8 and 16 and other PLL blocks. Improved the PN performance.

Involved with design of a CMOS charging management chip for mobile applications. Designed voltage and current references, comparators and power management circuits

Designed peripheral and analog interface circuits for MRAM chip in 45 nm CMOS technology. Designed blocks included Class AB buffers, ring oscillators and DDR interface.

Microtune was a spin-off from Cirrus Logic with industry first monolithic tuner. Responsible for realization of an industry-first monolithic cable TV-tuner. Involved in system design and implementation of BiCMOS LNAs, VGAs, mixers and phase-shifters. Supervised a team of 8 design-engineers and support personnel. Duties included defining and executing the design schedule, reviewing the technical specifications, consulting on circuit and system design, leading design-reviews, maintaining relations with prospective customers, interacting with foundry and packaging. Involved with recruitment of technical personnel, purchasing of equipment, software licensing and preparing patent applications.

Designed several BiCMOS gm-C filters equipped with automatic frequency- and Q-tuning. Involved with the design of a VHF/UHF TV tuner and its blocks including low-noise amplifiers and mixers.

Involved with design of a BiCMOS analog channel for a digital-video receiver including variable-gain amplifiers gm-C filters. Designed a high-speed transconductor for a mass-storage channel filter.

Together with 3 other engineers developed a new clocking technology in 28 nm CMOS with ultra high-accuracy and mitigated aging. The clock reference was targeted for 10 ppm accuracy and 5 ppm of aging. Several state of the art new technologies have been developed and patented. The work was funded from NSF SBIR grants.

* Design of 850 Ms/s and 8 Gs/s clock distribution systems in a 16 nm CMOS fin process. * Developed clock distribution system consisting of buffers, multiplexers and transmission lines. * System and circuit design for a novel K, Ka and V-band sub-sampled transceiver.

Contributed to the design of a 60 GHz 802.11ad transceiver chip in 130 nm BiCMOS technology Designed 20/60 GHz frequency multiplier, RX adjacent channel filter and LO distribution scheme

Tasked to convert a part of a DDR form a planar 20 nm into 16 nm fin CMOS. The circuitry included a self-calibration resistor ladder DAC and other blocks for an optimum biasing of DDR.