Adam Nagao

Adam Nagao

Technical Project Lead @ NVIDIA

Country

United States

City

Austin

Industry

Semiconductors

Skill

TDR, Electromagnetic Interference (EMI), Electrical Engineering, Printed Circuit Board (PCB) Design, Electromagnetic Compatibility, Controlled Impedance, Signal Design, connector design, package layout, Siwave, ANSYS HFSS, Vector Network Analyzers (VNA), Signal Integrity, cadence APD

Experience

NVIDIA

Technical Project Lead

NVIDIA

LinkedIn
2025-9 - Present · 1 yr 1 mo

— Responsible for interposer/RDL layout — Help review and sign off on RDL designs

Enfabrica

Packaging Manager Hardware

Enfabrica

LinkedIn
2024-9 - 2025-9 · 1 yr 1 mo

Mountain View, California, United States

Packaging manager. Responsible for package design/tapeout.

AMD

Senior MTS Analog Design Engineer

AMD

LinkedIn
2022-6 - 2024-9 · 2 yrs 4 mos

Austin, Texas, United States

Simulated/optimized package and PCB components for PCIE Serdes structures Worked on automation flow for package/pcb extraction of electrical models Responsible for end-to-end characterization of PCB/packages

Broadcom

Package Design Engineer

Broadcom

LinkedIn
2021-6 - 2022-6 · 1 yr 1 mo

Fort Collins, Colorado, United States

Responsible for package design for custom ASICs for data-centers Responsible for validating power/signal integrity of all signals/power nets Customer support for custom ASICs Responsible for ensuring ASIC design to tape out stage 5nm/7nm 112G PAM4 Serdes designed

I-PEX

Signal Integrity Engineer

I-PEX

LinkedIn
2017-4 - 2021-6 · 4 yrs 3 mos

Austin, Texas, United States

Developed high frequency MCX/Twin-ax cable connectors for server/supercomputing, and 5G applications Performed simulations for high speed mini board-board connectors showing performance up to 50Gbps (NRZ) Designed a custom 0.4mm and 0.5mm SMT pitch cable connector with 112G PAM4 performance.

Hirose Electric Americas

Signal Integrity Engineer

Hirose Electric Americas

LinkedIn
2011-9 - 2017-4 · 5 yrs 8 mos

San Jose, California, United States

PCB layout using Cadence Allegro 25Gbps designs High frequency measurements with VNA/TDR/Oscilloscope (Up to 67GHz) Experience with high speed designs (PCIE,USB) Performed 3D full wave simulations (HFSS/CST/SI Wave) and correlated data with de-embedded measurement Created 3D models with 3D cad software (CoCreate)

Education

Texas A&M University

Texas A&M University

LinkedIn

Electrical and Electronics Engineering

2008-9 - 2011-8 · 3 yrs

Adam Nagao's Contact Information

Email

******@***.com

Phone

(**) *** ****

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