Adam Courchesne

GPU Design Engineer/Manager - Graphics Subsystem @ Qualcomm

About

GPU Design Engineer/Manager with 25+ years of experience in GPU and ASIC design. I specialize in novel hardware architectures, scalable RTL development, and using automation to accelerate debug and root‑cause analysis. I lead while staying hands‑on, focusing on designs that balance performance, correctness, and long‑term maintainability.Specialties: * GPU Architecture and Design* IEEE 802.3 Ethernet* Verilog/SystemVerilog/VHDL Design* Defining efficient and scalable RTL development and coding methodologies* Synthesis, Static timing, Front-end processing* ASIC/FPGA Development* C/C++/Perl/Python/Java* OpenGLAdditional experience in:* Emulation* Embedded Systems* Computer GraphicsGPU* Reverse Engineering

Country

United States

City

Springfield

Industry

Semiconductors

Skill

Verilog, ASIC, OpenGL, C++, Atmel AVR, Microchip PIC, Xilinx, Altera, Reverse Engineering, VHDL, IEEE 802.3, Ethernet IP, Debugging, Static Timing Analysis, Embedded Systems, Linux, TCL, Ethernet, Embedded Software, Functional Verification

Experience

GPU Design Engineer/Manager - Graphics Subsystem

Qualcomm

2013-5 - Present · 13 yrs 5 mos

Boxborough MA

Development of the Render Backend subsystem Lead Developer of the Texture Pipeline processing unit within the Adreno GPU system (A5X, A6X, A7X series GPUs) Lead Developer of the L2 Flag Cache for UBWC texture compression/decompression Focusing heavily on: * Inter-shader context state management * Texel coordinate mapping/processing * High Order Texture Filtering * Texture processing for AR/VR * UBWC L2 Flag cache development * ASIC front-end process improvement and automation

Digital ASIC Core Developer

IBM

1997-6 - 2013-5 · 16 yrs

Burlington, Vermont Area

Digital Logic Design of Soft, Hard, and Synthesizable ASIC Cores. Responsibilities include core Architecture, Design, Synthesis and Timing, and Testability analysis. Majority of designs have been for use in high-speed Ethernet applications. Have also designed cores for Infiniband, LCD controllers, and bus protocol adapters. Synthesizable Methodology team lead. Define and support methodology for developing and releasing Synthesizable IP to ASIC and OEM customers.