Abelardo J.

Edge HW/SW Acceleration

- Developed a real-time streaming JPEG XS encoder/decoder kernel in CUDA for OrinX (Ampere). Optimized the encoder to run on the OrinX GPU using NSight Compute and NSight Systems, achieving JPEG XS encoding under 5msec for an 8MP Bayer BGGR 16-bit per pixel image. Used the Roofline model for performance analysis to evaluate the suitability of implementing JPEG XS encoder on OrinX GPU, DSP (PVA), and ARM CPU (A78AE). Delivered the JPEG XS encoder as a library and integrated it into the ROS node for real-time image processing and transmission. - Performance evaluation of PyTorch SDPA, and performance comparison FA v3 vs CUTLASS Blackwell Multi-head Attention vs manually-assembled TensorRT multi-layer engine on Nvidia Thor U. Used different configurations for Q, K, V including short Q query length for autoregressive decoder (inference) - Implemented tiled-GEMM (General Matrix Multiply) kernel using int8/int32 support on Tensilica Q7 DSP, including saturation support. The kernel was developed using a generic SIMD API (inspired by Google Highway) to leverage the Q7 DSP's vector capabilities while enabling portability and parity checking with a functionally equivalent ARM vectorized implementation. - Developed Linux drivers (`rpmsg`, `remoteproc`, `virtio`) for Tensilica Q7 DSP SoC accelerators (hosted on ARM CPU), adding `rpmsg` driver support for importing `DMA-BUF` for zero-copy data transfers. Supported performance counters with the `perf` event Linux kernel API to profile DSP usage. Also wrote a Performance Monitoring Unit (PMU) driver for the Tensilica DSP, enabling detailed performance tracking and optimization.

1. Development of AI/ML kernels on Arm GPU using OpenCL and Neon intrinsics. 2. Performance analysis and interconnect modeling for AI streaming pipelines using the CNI700 (NI-700) fabric. Conducted simulation and traffic validation with FastModels and Socrates, optimizing MCN, ASNI, and DSU flows under realistic AI-inference camera workloads.

1. Benchmarking of MLPerf, PageRanking, MySQL on premise and on AWS Azure and Google cloud 2. Capture performance counters, optimize kernels and application tuning and analysis 3. Work with FastModels (functional models) and Socrates (cycle-accurate approximate models)

1. Benchmarking and performance analysis of different suites like SPEC2017, SPEC2006, SPECJBB2015, BoringSSL on Nvidia ARM platforms. 2. Capture of different performance counters to measure branch miss prediction, cache misses 3. Generation of processor checkpoints and instructions traces using functional system simulators like Simics and Tegrasim. 4. Generation of instruction traces using DynamoRIO.

1. Performance analysis of Intel Streaming DMA runtime/kernel drivers for Intel Programmable Acceleration Cards (PAC, Arria 10 FPGA) on Linux using Intel vTune and Linux 'perf' tool. After pointing Intel TBB dequeue causing user space application to enter in lengthy interruptible sleep state (semaphore based implementation lead consumer thread to be placed in sleep state and OS to use sched_yield), I rewrote the Intel Streaming DMA drivers to utilize userspace futexes instead of Intel Thread Building Block Semaphores, achieving an 25% bandwidth increase when using 4kB DMA transfers over PCIe x8 bandwidth. 2. Implemented C++ abstraction layer on top of both Intel API for FPGAs (Intel OPAE) and Xilinx API for FPGAs (Xilinx OpenCL/XRT). Implemented abstraction layer automatically handled object allocation/deallocation through lifetime events of the wrapping C++ object s (e.g. automated buffer deallocation when exiting current scope; device handle closing and deallocation when exiting current scope, etc). 3. Implemented streaming DMA accelerator prototype using Xilinx SDAccel 2019.1 and a Xilinx Alveo U200 card

Taught class on High Performance Computing Acceleration using Intel Programmable Accelerator cards (PAC) and OpenCL to 250 students among graduate school and multi-disciplinary researchers

1. Developed design patterns-based OOP software for HW/SW simulation environment using SystemVerilog Dynamic Programming Interface (DPI) and C++. Cosimulation environment supports commercial RTL simulators (Synopsys VCS and Mentor Modelsim/Questa) and utilizes Linux IPC/RPC to communicate with a client C++ application. 2. Develop a Clang-based AST parser (consumer/visitor/rewriter) to generate C implementation files from C and/or Verilog header files. 3. Worked on Linux driver development for FPGA-based PCI devices, including device tree and device overlays for embedded platforms. Performed Linux kernel and driver debugging using GDB and KVM/qemu virtualization. Familiar with PF/VF for virtualization. 4. Experience of continuous integration methodology using Google Test/Teamcity/- Travis 5. Implemented driver security architecture for a Linux PCI driver (AAL), including X.509 certificate parsing, SHA256 digest generation and RSA-2048 signature checking using the 2048-bit public key. Performed the implementation in both Linux kernel space and user space. 6. Part of the team that design and implemented the open-source Intel C/C++ API for the Xeon+Altera platforms (Open Programmable Accelerator Layer, OPAE) - https://github.com/OPAE/opae-sdk/blob/master/AUTHORS 7. Developed sample SystemVerilog RTL code for accelerators on Xeon+FPGA hybrid architectures (Skylake/Broadwell).

1. Wrote Verilog models of Intel Custom Foundry standard cells with timing back annotation for logic synthesis using Synopsys Design Compiler. Performed hierarchical synthesis of digital logic modules in Synopsys Design Compiler and Primetime Static Timing Analysis for Intel Foundry 22nm and 14nm. 2. Experience with both Synopsys HSpice and Cadence Spectre simulation for standard cell characterization. 3. Designed and implemented GUI-enabled Python/TCL software for automated floor- planning and routing of 22nm, 14nm digital standard cells (gates). Developed floorplanner performed design space exploration for optimizing different process-specific constraints (heat- and power-aware standard cell placement). I developed software GUI using PySide (Qt) and software backend using a combination of Python oaScript (OpenAccess), Synopsys TCL scripting and Cadence Skill 4. Implemented Cadence Skill/Skill++ pCells and scripts for automated generation of front-end and back-end layout structures. 5. Layout-level power analysis using Apache Totem and Apache Redhawk. 6. Experience with Mentor Calibre SVRF and Synopsys IC Validator physical verification tools for verifying DRC correctness on generated layouts.

- Student leader of FPGA Partial Reconfiguration Group of National Science Foundation (NSF) at the Center of High-Performance Reconfigurable Computing (CHREC) - Project management (over group of 6 students) - Continuous preparation of business presentation for funding CHREC industry members. - Implementation of partially-reconfigurable embedded systems on Virtex VLX110T (OpenSPARC board device) - In-depth experience with Xilinx synthesis, place-and-route utilities (including Vivado/ISE-independent binary utilites) - Hardware modeling and implementation of Kalman filters (application: real time target-tracking) using VHDL and Xilinx FPGAs. Simulation and calculation of Kalman filter coefficients using Matlab. - Development of C-based Linux-drivers to access partially-reconfigurable hardware modules. - Development of C-based Linux daemons (networking services) running on MicroBlaze embedded microprocessor. - Development of a real-time embedded FPGA-based acquisition system, including development of VHDL interface with OV2722 2-megapixel image sensor and a FT234XD USB interface. - Experience with High-Level Synthesis using /Impulse-C/. - Development of C/C++ and Python fully object-oriented-programming based software, including usage of MPI (message passing interface) API and GTK toolkit. - Six research publications from performed work (including /Design, Automation and Test in Europe/, FPL, and Reconfig conferences)

Taught courses of Artificial Intelligence, Computer Architecture, Digital Signal Processing, Algorithms, Object Oriented Programming. Research on Digital Architecture Design, Digital Signal Processing and Finite Element Method Analysis. 2nd Place on Peruvian National contest for Electronics Engineers INTERCON 2001.

(CID-FIEE-UNI). Developed the hardware and software of a PCI gamma camera acquisition board by request of the National Institute of Neoplassic Illnesses (INEN), Lima-Peru. The hardware was implemented using a Xilinx Spartan2E FPGA and the software using Visual C++. The digital part of the system was implemented using VHDL and Xilinx ISE and the PCB board was designed using OrCAD Layout. Developed a FIR filter using Distributed Arithmetic in a Spartan3E FPGA. The filter took signals from a PCM 13-bit Motorola MC145483 audio codec. Development of the printed circuit board using OrCAD. Design and implementation of a digital acquisition system for the gyroscope of a Macci MB 339 aircraft using a Parvus PC 104 Space PC computer.

NSF Center for High Performance Reconfigurable Computing. F4 (Partial Reconfiguration) Group Leader; Doctoral Qualifying Examination passed in January 2009. Latinamerican and Caribbean Fellowship.

VLSI Design Automation, embedded system design.

3rd best in the class (over 60 students)

High School student, Swimming, Math, Literature